Hello~
Please look at the following codes:
[code]//TIM8,PC6 PC7
RCC->APB2ENR |= 1<<1; //TIM8 timer enable
RCC->AHB1ENR |= 1<<2; //GPIO port clock enable

GPIOC->MODER &= 0xFFFF0FFF; //PC6，PC7 set to be reuse pattern
GPIOC->MODER |= 0x0000A000;

GPIOC->AFR[0] &= 0x00FFFFFF;
GPIOC->AFR[0] |= 0x33000000;

TIM8->ARR = 0xFFFF;
TIM8->PSC = 0;
 
TIM8->CCMR1 &= 0xFCFC;  //CC1 pass set to be input， IC1 map on TI1 ,CC2  pass set to be input， IC2 map on TI2 
TIM8->CCMR1 |= 0x0101;           
 
TIM8->CCER  &= 0xFFDD;
TIM8->CCMR1 &= 0x0F0F;   //no flagging
 
TIM8->SMCR  &= 0xFFF8;
TIM8->SMCR  |= 0x0003;
 
TIM8->CR1 |= 1<<0;     //enable counter

//TIM1,PA8 PA9
RCC->APB2ENR |= 1<<0; //TIM1 time enable
RCC->AHB1ENR |= 1<<0; //GPIOAport clock enable

GPIOA->MODER &= 0xFFF0FFFF;      //PA8，PA9 set to be reuse pattern
GPIOA->MODER |= 0x000A0000;  
 
GPIOA->AFR[1] &= 0xFFFFFF00;
GPIOA->AFR[1] |= 0x00000011;

TIM1->ARR = 0xFFFF;
TIM1->PSC = 0;
 
TIM1->CCMR1 &= 0xFCFC;  //CC1 pass set to be input， IC1 map on TI1 上,CC2 pass set to be input， IC2 map on  TI2 上
TIM1->CCMR1 |= 0x0101;           
 
TIM1->CCER  &= 0xFFDD;
TIM1->CCMR1 &= 0x0F0F;   //no flagging
 
TIM1->SMCR  &= 0xFFF8;
TIM1->SMCR  |= 0x0003;

TIM1->CR1 |= 1<<0; //enable counter[/code]

As the codes we can see,TIM8 can counte as normal but TIM1 has no ** count and the DIR changes from up to now. I don’t know if is the USART1_TX of PA9 wrong? Or the reason occurred by hardware--STM32F407 ? Well, this is the datasheet of STM32F407: [http://www.kynix.com/uploadfiles/pdf8798/STM32F407VET6.pdf](link url) ,you can see more details about the hardware.

Please help! Thanks.
Best wishes~